HalpCmciSetProcessorConfigAMD
CHAR __fastcall HalpCmciSetProcessorConfigAMD(INT64 rcx0, CHAR a2, INT64 a3){
INT64 v5;
__int64 v6;
INT64 MsrMisc;
unsigned int v8;
unsigned int v9;
unsigned int v10;
unsigned int v11;
INT64 v12;
INT64 v13;
unsigned int v14;
__int64 v15;
INT64 v16;
INT64 v17;
INT64 v18;
__int64 v19;
INT64 v20;
INT64 v21;
INT64 v22;
INT64 v23;
INT64 v25;
unsigned int v27;
v5 = rcx0;
if( HalpMcaScalableRasSupported )
{
v6 = ((__int64(__fastcall *)(INT64, __int64, _QWORD))HalpWheaReadMsr)(a3, 3221226512i64, 0i64);
HalpWheaWriteMsr(a3, 3221226512i64, (a2 != 0 ? 0x1000ui64 : 0) | v6 & 0xFFFFFFFFFFFF0F0Fui64 | (a2 != 0 ? 0x20 : 0));
}
LOBYTE(MsrMisc) = HalpMcaNumberOfBanks;
if( !HalpMcaNumberOfBanks )
{
MsrMisc = __readmsr(0x179u);
HalpMcaNumberOfBanks = MsrMisc;
}
v8 = (unsigned __int8)HalpMcaNumberOfBanks;
v9 = 0;
v27 = (unsigned __int8)HalpMcaNumberOfBanks;
if( HalpMcaNumberOfBanks )
{
v10 = -1073733622;
v11 = 1027;
do
{
MsrMisc = HalpWheaReadMsrMisc(a3, v9);
v25 = MsrMisc;
v13 = MsrMisc;
if( MsrMisc < 0 )
{
if( BYTE3(MsrMisc) )
{
if( HalpMcaScalableRasSupported )
v14 = v10;
else
v14 = 8 * BYTE3(MsrMisc) - 1073740800;
v15 = 4i64;
do
{
v16 = ((__int64(__fastcall *)(INT64, _QWORD, _QWORD))HalpWheaReadMsr)(a3, v14, 0i64);
LOBYTE(v17) = a2;
HalpCmciSetProcessorMiscConfigAMD(rcx0, v14++, v16, v17, a3);
--v15;
}
while( v15 );
v13 = v25;
v8 = v27;
v5 = rcx0;
}
v18 = v10 - 7;
if( !HalpMcaScalableRasSupported )
v18 = v11;
LOBYTE(v12) = a2;
LOBYTE(MsrMisc) = HalpCmciSetProcessorMiscConfigAMD(v5, v18, v13, v12, a3);
if( HalpMcaScalableRasSupported )
{
v19 = ((__int64(__fastcall *)(INT64, _QWORD, _QWORD))HalpWheaReadMsr)(a3, v10 - 6, 0i64);
HalpWheaWriteMsr(a3, v10 - 6, v19 & 0xFFFFFF9FFFFFFFFFui64 | -(__int64)(a2 != 0) & 0x2000000000i64);
v20 = ((__int64(__fastcall *)(INT64, _QWORD, _QWORD))HalpWheaReadMsr)(a3, v10, 0i64);
LOBYTE(v21) = a2;
HalpCmciSetProcessorMiscConfigAMD(v5, v10, v20, v21, a3);
v22 = ((__int64(__fastcall *)(INT64, _QWORD, _QWORD))HalpWheaReadMsr)(a3, v10 + 1, 0i64);
LOBYTE(v23) = a2;
LOBYTE(MsrMisc) = HalpCmciSetProcessorMiscConfigAMD(v5, v10 + 1, v22, v23, a3);
}
}
++v9;
v11 += 4;
v10 += 16;
}
while( v9 < v8 );
}
return MsrMisc;
}Referenced by:
HalpCmciPollProcessor
HalpCmciResetStateAMD
HalpCmciSetProcessorConfig